Menlo Micro Financial Model

• Core product: The Ideal Switch - a MEMS switch fabricated on 8-inch glass wafers using a proprietary metal alloy beam and Through-Glass-Via (TGV) packaging.
• Tagline / thesis: "Milliwatts-to-kilowatts, DC-to-light" - a single platform spanning RF switching and AC/DC power switching.
• Key performance claims vs. electromechanical relays (EMR): 100x less power (<1mW vs >100mW), 100x higher linearity (>85dBm vs 60dBm), 1000x faster switching (<10µs vs 10ms), 1000x longer life (>3B vs <3M cycles), >99% size reduction (0.006–0.6 cm³ vs 1–71 cm³).
• Key performance claims vs. solid-state (SS): 100x better linearity, >0.5dB lower insertion loss (0.2dB vs 0.7dB), 10x less power, 85% less on-resistance (>30mΩ vs 200mΩ), no heatsinks needed.
• Product configurations: Core switch, switch with integrated controls, multi-die switch matrix, RF System-on-Glass. Unit cell: 50µm × 50µm.
• Spin-out origin: GE Global Research began MEMS circuit-breaker program in 2004; Menlo Micro spun out in 2016 to commercialize IP beyond GE verticals.

• SAM target: $20B+ by 2023, spanning RF relay, RF solid-state, GP relay, GP solid-state, and Power relay segments across 6 end markets.
• End-market SAM breakdown (read from stacked bar chart, approximate):
• Medical: ~$150M
• Aero & Defense: ~$200M
• Test & Measurement: ~$600M
• Consumer: ~$750M
• Telecom: ~$1,500M
• Power IoT: ~$20B+ (dominant, future product; shown as a single gold bar at full scale)
• Today (2020) addressable: RF and general purpose switching. Power IoT/AC/DC is the future expansion.
• Source: Frost & Sullivan market reports + internal Menlo estimates.

• Unit sales of switch ICs to OEM customers. B2B direct sales model implied (no mention of distribution channels or marketplaces).
• Go-to-market today: Qualified GE supplier; first design win is GE Healthcare MRI machines (each MRI replaces >100 PIN diodes with Ideal Switch units).
• Expanding to: Defense, Communications, Test & Measurement via follow-on contracts.
• Revenue recognition: Per-unit shipments (standard semiconductor component model).
• COGS levers: 8-inch wafer fab (4x die/wafer vs 4-inch), volume pricing at commercial fab, scalable test infrastructure.

• Units shipped: >100K Ideal Switches shipped to GE Healthcare (Fortune 100 first customer).
• Customers: At least one confirmed production customer (GE Healthcare). Defense, Comms, T&M described as contract-stage.
• Fab capacity 2017: 180 wafers/year (8-inch equivalent); 100K units/year test capacity.
• Fab capacity today (Oct 2020): 6K wafers/year (Menlo allotment); >10M units/year test capacity; 4x die/wafer improvement from 8-inch switch.
• Capital raised: >$77M since 2016 founding.
• Investors: Paladin Capital Group, GE Ventures, Corning, Microsemi.
• Certifications: ISO 9001:2015 certified; qualified GE supplier.

Design-level structural notes only:

• COGS is wafer-based: cost per die × dies/wafer, scaled by wafer volume. 8-inch fab materially reduces COGS vs prior 4-inch setup.
• Test cost is a significant COGS component (>10M units/year infrastructure now in place).
• Heatsink elimination and size reduction generate OEM-level BOM savings; value-based pricing opportunity.

• Direct competition: Electromechanical relays (Omron, TE Connectivity, Panasonic) and solid-state switches (PIN diodes, GaN, CMOS).
• Moat: Proprietary metal alloy beam science licensed from GE (>100 years of high-voltage metallurgy); Corning glass substrate and TGV partnership; unique combination of conductor-grade ON performance with semiconductor-scale size/cost.
• IP: GE-originated core IP acquired at spin-out; ongoing internal development.
• Barriers: MEMS at scale is notoriously hard; the fab transition from 4-inch R&D to 8-inch commercial is itself a multi-year moat.
• No named direct competitors to the Ideal Switch platform are cited. Deck positions it as a category creation.

• CEO: Russ Garcia - prior CEO WiSpry, CEO uNav; EVP Microsemi; TI, Silicon Systems, Hughes.
• Co-Founder / CTO: Chris Keimel - former Senior Research Scientist, GE Global Research Center.
• Co-Founder / SVP Marketing: Chris Giovanniello - VP GE Ventures, Teradyne.
• CFO: Mark Czepiel - prior CFO WiSpry (RF MEMS semiconductor).
• SVP Manufacturing: Jeff Baloun - GM Deca Technologies, CEO Imbera, GM Unisem.
• SVP Sales: Lew Boore - VP Silanna, Cavendish Kinetics, WiSpry, Agilent, M/A-COM.
• Board: Russ Garcia (CEO); Paul Conley PhD (Paladin Capital); Marianne Wu (40 North Ventures); John Major (former Broadcom Chairman); Jim Cable (former pSemi Chairman & CTO).
• Advisors include: Rich Simoncic (SVP Analog, Microchip Technology); Kari-Pekka Wilska (former Nokia Americas President); Michael Idelchik (former VP Advanced Technology, GE Global Research).

• Archetype + why: Semiconductor component manufacturer revenue model - unit shipments × ASP by product family, with wafer-based COGS and standard fab-scale operating leverage. This is a deep-tech hardware company with discrete unit economics (wafers → die → tested units → packaged switches → customer shipments). A 3-statement model is appropriate, but the primary analytical engine is a bottoms-up unit/volume/revenue build by end market, paired with a wafer-economics COGS model. Not SaaS, not marketplace, not subscription.

• Forecast horizon & granularity: 5 years (2021–2025), quarterly for years 1–2, annual for years 3–5. Deck references a "5-year plan" explicitly.

• Key drivers & assumptions:

*Revenue side:*

• Units shipped by end market (Medical, Aero & Defense, T&M, Telecom/Comms, Consumer, Power IoT): ramp from >100K in 2020 base; scale trajectory - production capacity of >10M units/year is the near-term ceiling
• ASP per unit by product family: - RF switch ICs typically $2–$10 ASP at this performance tier; power switches could be $5–$25. Must be confirmed; no ASP in deck
• Revenue mix shift: RF/GP switching today → Power IoT future; higher ASP likely for power products
• Design win conversion rate and ramp timeline per customer: - typical semiconductor design-win-to-revenue cycle is 12–24 months

*COGS / manufacturing:*

• Wafers/year: 6K (current allotment); scales with revenue ramp via fab capacity negotiation
• Die per wafer: 8-inch wafer = 4x die vs 4-inch; further improvements from design shrink
• Yield rate: - start at 80%, improve to 90%+ as process matures; standard for MEMS at commercial fab
• Test cost per unit: - infrastructure now in place for >10M units/year; costs per unit decline with volume
• Gross margin: - target 50–60% at scale, typical for specialty semiconductor ICs; early ramp likely 20–35%

*Opex:*

• R&D: significant - new product configurations (matrix, RF SoG, Power IoT) require continued investment; ~30–40% of revenue in early years
• Sales & Marketing: B2B enterprise sales motion; small field team; ~10–15% of revenue
• G&A: ~8–12% of revenue
• Headcount: - lean team implied by executive bios; add engineering and sales headcount per revenue tier

*Balance sheet / cash:*

• $77M+ raised to date; runway position and burn rate not disclosed
• CapEx: - fab allotment model (no wafer fab ownership); primary CapEx is test equipment; relatively asset-light vs. owning a fab
• Working capital: - semiconductor B2B typical 60–90 day receivables, 30–60 day payables

• Scenarios (Base / Bull / Bear):
• *Bear:* Power IoT product delayed 2+ years; design-win ramp slower than expected; ASP compression from competition; gross margin stays below 35% through 2025
• *Base:* GE Healthcare volumes grow, 2–3 new defense/comms design wins by 2022, Power IoT products enter sampling 2023, gross margin reaches 45–50% by 2024
• *Bull:* 5G infrastructure cycle drives large Telecom win; Power IoT qualifies at a major industrial OEM; fab capacity expanded to 20K+ wafers/year; gross margin >55% by 2024

Flex variables: unit ramp by end market, ASP by product family, yield, wafer allotment, and Power IoT launch timing.

• Required sheets / outputs:

1. Assumptions dashboard (all drivers in one place, tagged DECK vs ASSUMED)
2. Unit volume build by end market (annual, then quarterly for near-term)
3. Revenue by product family (RF switch, GP switch, Power switch)
4. Wafer economics / COGS model (wafers → die → yield → tested units → packaged; cost/wafer, cost/die, cost/unit, blended gross margin)
5. Operating expense model (R&D, S&M, G&A, headcount)
6. Income statement (3-statement)
7. Balance sheet (3-statement)
8. Cash flow statement (3-statement) with cash runway
9. Scenario toggle (Bear / Base / Bull) on key drivers
10. SAM penetration tracker (units shipped vs. market size by vertical) - ties to slide 20 market data