NU

Nuvia Financial Model

• Custom-designed server-class CPU/SoC running the ARM ISA, built from scratch on a leading-edge process node.
• Target workloads: single-threaded and multi-threaded data center performance, plus a full reference platform for system partners.
• Future platform extensions into AI, networking, and storage.
• Core thesis: x86 server CPU innovation has stagnated (incremental perf gains, slowing Moore's Law, complex architectures misaligned with customer needs); leading ARM mobile SoCs are closing the performance gap with x86 servers, creating an opportunity to leapfrog with a ground-up server ARM design.
• NUVIA targets the white space above all existing ARM SoC curves - slide 12 shows a blue shaded "NUVIA target zone" peaking at ~2,000+ single-core Geekbench 5 score at 1–5W idle-normalized power, well above Apple A13/A12Z (~1,300/1,100) and all Intel/AMD/Qualcomm parts at equivalent power.

Not explicitly stated in deck. Implied model:

• Fabless semiconductor: design proprietary CPU/SoC; manufacture via third-party foundry (leading-edge process node implied).
• "Targeted customer engagement approach with partners capable of deploying new system architectures" - suggests direct engagement with hyperscalers / ODMs / OEMs, not a broad retail channel.
• No ASP, volume, or royalty/licensing structure disclosed.

• No revenue or customer figures in deck. Company is pre-product (chip design stage as of Sept 2020).
• Performance context from benchmarks shown:
• x86 (leading): ~5,000 5-yr perf score in 2014, plateauing ~6,200 by 2018–2019.
• Leading ARM SoC: ~1,800 in 2014, growing to ~5,700 by 2019 - rapidly converging with x86.
• Rest of ARM SoCs: ~1,000 in 2014, ~3,300 by 2019.
• NUVIA's target (Geekbench 5 perf/watt): Single-core score >2,000 at <5W idle-normalized power - exceeds all benchmarked parts at equivalent or lower power envelopes.
• Team: 200+ people hired with 20+ years average experience; 3 named co-founders hold combined 102+ issued patents.

• Competitors named: Intel x86 (Sunny Cove, Skylake), AMD Ryzen (Zen 2), Qualcomm S865 (ARM A77), Apple A13/A12Z.
• Competitive dynamic: x86 server innovation is incremental; ARM mobile leaders (Apple) dominate perf/watt in mobile but have not built server-class designs.
• Moat claimed: ground-up custom architecture (not a core license modification), led by ex-Apple/Qualcomm/ARM silicon veterans, deep patent portfolio (102+ issued for 3 founders alone), heterogeneous integration as the next 50-year innovation axis.
• Series A investors include Dell Technologies Capital (strategic signal: data center OEM validation).

• Co-founders: Gerard Williams III (CEO/President, ex-Apple, Qualcomm - 38 issued + 8 pending patents); Manu Gulati (VP SoC Engineering, ex-Apple, Qualcomm - 58 issued + 6 pending); John Bruno (VP System Engineering, ex-Google, AMD, Apple - 6 issued).
• 200+ person team, 20+ years avg experience.
• Series A complete - investors: WRVI Capital, Capricorn Investment Group, Dell Technologies Capital, Mayfield, Nepenthe LLC.
• Series B described as "coming soon". No dollar amounts for either round disclosed in deck.

• Archetype + why: Fabless semiconductor 3-statement + milestone-gated opex model. NUVIA is pre-revenue, pre-product; no operating revenue or unit economics to model. The right model is a burn/runway model built around R&D headcount spend (the dominant cost), supplemented by a revenue ramp scenario starting at first product revenue (est. 2022–2023 at earliest given chip development timelines). This is analogous to a deep-tech startup model - opex-driven through tape-out, then a capital asset/revenue ramp phase.
• Forecast horizon & granularity: 5 years (2020–2025), monthly for the burn/runway model through first revenue, then annual for the revenue ramp. Monthly granularity matters for cash management given multi-year pre-revenue period.
• Key drivers & assumptions:
• Headcount: 200+ as of deck date; avg fully-loaded engineer cost ~$250–300K; grows to ~400–600 by tape-out.
• R&D opex: dominates P&L; capex light (fabless - no fab ownership).
• Tape-out cost: $5–20M per tape-out on leading-edge node (e.g., TSMC 5nm/7nm).
• Time to first silicon: ~2–3 years from founding (founded 2019, so 2021–2022).
• Time to first revenue: 1 year post first silicon validation (~2022–2023).
• ASP: server CPUs sell at $500–$3,000+ per unit to hyperscalers/OEMs.
• Initial unit volumes: small (pilot / qualification batches), scaling rapidly once design wins secured.
• Gross margin at maturity: 50–65%.
• Series B raise: assumed 2020–2021, size $150–300M.
• Scenarios (Base / Bull / Bear - which variables flex):
• Bear: tape-out delayed 12 months, design win with only one hyperscaler partner, ASP at low end, slower volume ramp → runway extends but revenue materially delayed.
• Base: first silicon 2021–2022, one anchor hyperscaler design win, ramp to meaningful revenue by 2023.
• Bull: Apple M-series disruption triggers faster hyperscaler urgency, two+ design wins, ASP at high end, acquisition interest from Qualcomm/Arm/hyperscaler before product launch. (Note: historically accurate - Qualcomm acquired NUVIA in March 2021 for ~$1.4B, before product launch.)
• Required sheets / outputs:
• `Assumptions` - all headcount, cost, timing, and pricing inputs.
• `Headcount Plan` - monthly by function (CPU arch, SoC, software, G&A), location, and fully-loaded cost.
• `P&L` - monthly opex (R&D dominant, then G&A); no COGS until product revenue.
• `Cash Flow` - burn rate, Series A/B tranches, runway months.
• `Revenue Ramp` (post-product) - unit volumes × ASP × gross margin by customer segment.
• `Balance Sheet` - simplified; key items are cash and equity raised.
• `Funding Waterfall` - Series A, Series B, exit scenarios (acquisition at $1–3B range given comparables).
• `Dashboard` - KPI summary: cash runway, burn rate, headcount, months to tape-out, months to revenue.